Interfacing AC Coupled Interconnect design with Rocket I/O compatible FPGA systems.
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Date
2006-12-19
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Abstract
As data rates continue to increase, there is an increasing need for reliable high-density, high-speed interconnect technologies. AC Coupled Interconnect provides a solution to this problem. The characterizing of high-speed systems in an efficient manner is an important issue and BER (Bit Error Rate) is one of the most important metrics utilized to characterize high-speed interconnect technologies.
In this thesis we have developed circuitry that interfaces AC Coupled Interconnect designs with FPGA based systems that compute the system BER. The FPGA uses Rocket IO transmitters and receivers to communicate with the test chip. Thus the understanding of Rocket IO signaling becomes important. Extensive simulations of the Rocket IO transmitter and receiver models provided by XILINX were carried out across all the process corners to characterize the system behavior accurately. The interface circuitry was designed using the TSMC 0.25 Micron process parameters, and the entire design is validated across a temperature spectrum of -40 C to 120 C and supply voltage of 2.25 V to 2.75 V. The complete self-test vehicle constitutes the FPGA and the test chip on a single PCB.
This system is evaluated based on jitter, signal swing and common mode voltage associated with the signal at the Rocket IO receiver input. HSPICE models for the Rocket IO transceivers provided by Xilinx allow us to simulate the entire system.
Simulations were carried out to study the impact of ESD on the coupling capacitor used in the ACCI design. HBM, MM and CDM ESD wave forms were generated in HSPICE using the standard circuit models provided. The simulation results were helpful to understand the amount of ESD protection offered by the coupling capacitor. Capacitance associated with ESD protection becomes a major area for concern with continuous device scaling. These simulations clearly point to the fact that the coupling capacitors used in the ACCI system helps to reduce the amount of ESD protection required. This in turn enables the use of smaller ESD protection circuits with lower capacitances.
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Keywords
CML, High-speed, SCL, Rocket IO, ESD, ACCI
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Degree
MS
Discipline
Electrical Engineering
