Instruction Cache Checkpoints Using Phase Tracking and Prediction
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Date
2005-12-30
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Abstract
The Memory wall is standing taller than ever. There is an ever growing imbalance between memory bandwidth and processor speeds. Due to these diverging rates most applications are limited by memory performance. Various aggressive techniques to hide memory latency have done little to hide this gap. Clearly, we will need better optimization techniques to bridge the gap between processor and memory speeds. In future it will be necessary for us to understand program patterns and behavior at run time, so that we can efficiently utilize various optimization techniques. Past research [10] has suggested that program's tend to have cyclic patterns of execution. They tend to execute in phases, which repeat over time. It is possible to efficiently capture, classify and predict phase based program behavior at run time [13].
We propose using Phase Tracking and Prediction to bridge the memory gap. We introduce the concept of Instruction Cache Checkpoints that exploit program behavior to prefetch into the Instruction Cache. The intuition behind this scheme is that since phase behavior can be predicted, we can effectively pre-fetch instructions according to phase transitions. We also propose a new improved Phase Prediction architecture based on phase run-lengths. We begin by studying and evaluating phase behavior in SPEC2k FP benchmarks. The observed phase behavior is then exploited by creating Instruction Cache Checkpoints that use prefetching based on phase changes. Detailed simulation of five of the SPEC 2k FP benchmarks show that using Instruction Cache Checkpoints gives us an average reduction of 17.8% in the number of Instruction Cache misses.
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Memory Wall, Instruction Cache Checkpoints, Cache Prefetching, Phase Prediction, Phase behavior, Phase Tracking
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Degree
MS
Discipline
Computer Science
