Low Power Interconnect Circuits using Silicon Carriers

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Title: Low Power Interconnect Circuits using Silicon Carriers
Author: Gadfort, Peter
Advisors: Paul Franzon, Committee Chair
Michael Steer, Committee Member
Rhett Davis, Committee Member
Abstract: Due to the ever-increasing complexity of the tasks that modern electronic devices are expected to carry out, many devices incorporate multiple chips linked via input/output pins and transmission lines on a single board in multi-chip modules. The interconnects between these chips are a large source of power drain due to the parasitic capacitance loading of the input/output pads on the chip and the transmission lines. <br/> By moving multiple chips onto the same substrate to form a "virtual" chip, the I/O pins and transmission lines used to connect the chips can be replaced with a silicon carrier and micro-bumps. By creating these "virtual" chips, incompatible technologies such as GaAs and silicon substrate can be merged into a single package. Using silicon carriers also allows for the use of fine-pitch interconnects down to 2 μm - built into the silicon carrier - which is a large improvement over current organic or ceramic packaging technologies. <br/> This work investigates a current mode circuit proposed by Zhang to achieve a significant power advantage over current signaling techniques and packaging technologies. This will be achieved by utilizing silicon carrier technology for the interconnects between integrated circuits. The interconnects can span the carrier from a few millimeters up to several centimeters depending the on the interconnect structure. By trading the bandwidth of the silicon carrier for length of the interconnect, various lengths can be chosen for the desired data throughput. Also, by trading noise margin for reduced power in the I/O circuits a significant power reduction in the circuits can be achieved. <br/> This work will show that a power reduction of 75%, for the power metric of power per gigabit per second, is possible over current organic packaging technologies and a standard driver, by using the improved driver and the silicon carrier interconnects. These circuits were designed in a predictive 45 nm process and the achieved bit error rates were on the order of 10<sup>-15</sup> errors/bit while operating at 4 Gbps.
Date: 2009-05-07
Degree: MS
Discipline: Electrical Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/2517

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