Considerations for Electrical Characterization of MOS Capacitors that Arise Due to Processing

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Title: Considerations for Electrical Characterization of MOS Capacitors that Arise Due to Processing
Author: Schrader, Michael John
Advisors: Richard Kuehn, Chair
Dennis Maher, Member
Veena Misra, Member
Abstract: The goal of this research was to determine the effects thatthe actual physical structure of an overlapped metal-oxide-semiconducter (MOS) capacitor and an etch bias have on the extraction of the gate-oxide thickness. Included in these concerns were the overlap of the field oxide by the gate electrode, the angle of the active-area sidewall, and the increase in size of the active area due to an etch bias. In addition, the growth of a contaminant layer, or ad-layer,on oxides that do not have a permanent gate-electrode was addressed. This ad-layer forms immediately after a wafer is exposed to the lab ambient and causes a significant increase (i.e., ~ 10%) in the apparent thickness of the oxide.The refinement of the total capacitance to the active-area capacitance uses measured data from Hg-gated capacitors on p-type Si wafers and Al / Poly-Si gated capacitors on both p- and n-type Si wafers. The effects of a non-vertical sidewall and an etch bias are addressed theoretically through the use of the classic treatment of capacitance. The capacitance-voltage characteristics from the MOS capacitors were used to extract the oxide thickness (tox).The extracted thickness was determined from a model-based methodology (i.e., the slope method) and a model-based analysis (i.e., NCSU's CVC model). It is shown that the effect of a non-vertical sidewall and an etch bias are negligible. The effect of the gate electrode overlap, while small, should be removed. It is also shown that a model-based analysis of the active-area capacitance characteristics results in a consistent oxide thickness over the range of capacitor areas that were available.The removal and re-growth of the ad-layer were investigated using current-voltage and capacitance-voltage characteristics from blanket oxides on both p- and n-type silicon wafers. The changes in these characteristics were quantified as the ad-layer grows over time. The C-V characteristics were analyzed using NCSU's CVC program in order to extract values for oxide thickness, flatband voltage, and interface trap densities. The ad-layer causes considerable inaccuracies in the model extraction of oxide thickness as well as the flatband voltage and interface trap density. Electrical and optical results on the p-type wafer both show that the ad-layer increases the apparent oxide thickness by ~ 0.25 nm and the electrical results show that the ad-layer shifts the flatband voltage by as much as 100 mV.
Date: 2001-07-31
Degree: MS
Discipline: Electrical Engineering

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