Functional Verification of an ALU Core applying the Constrained Random approach
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Date
2003-06-04
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Abstract
ASIC complexity is increasing so rapidly that designer productivity is not coping with the growth. Verification presents about 60-70% of the total design effort and only advances in verification methodology can improve the time to market considerably. Directed tests and 'golden' reference files will soon become the primitive tools of the modern test environment. Verification engineers are consequently looking towards new methodologies like Constrained-Random approach to reduce test bench development time, and speed-up the time it takes to achieve complete verification of their ASIC or SoC. Test bench automation tools for constrained-random stimulus generation and functional coverage create tests for corner cases that even engineers who designed the system may not anticipate and hence find bugs early in the development cycle. This thesis describes the study and implementation of the Constrained-Random concept in the Functional verification of a 32-bit ALU core using Specman.
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Keywords
Bugs, Testplan, Escape Analysis, Regression, Reference model, Golden vectors, Patrick Hamilton, Functional Coverage, Code Coverage, Assertions, Testbench, Testcase, Functional Verification
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Degree
MS
Discipline
Computer Engineering
