IA-64 Code Generation

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Title: IA-64 Code Generation
Author: Rao, Vikram S.
Advisors: Dr. Tom Conte, Chair
Dr. Eric Rotenberg, Co-chair
Dr. Douglas Reeves, Co-chair
Abstract: This work presents an approach to code generation for a new 64-bit ExplicitlyParallel Instruction Computing (EPIC) architecture from Intel, called IA-64. Themajor contribution of this work is the design of a machine independent optimizer,munger, that transforms code generated originally for a Very Long Instruction Word(VLIW) processor, called Tinker, to one that can run on the IA-64 architecture.The munger does this transformation by reading in a set of rules that specify amapping from Tinker specific code to IA-64 specific code. Th aim is to do thistransformation outside the compiler back-end, thereby being able to take advantageof any optimizations that the back-end might perform on the code. This would alsopreclude rewriting the existing back-end significantly, to support the new architecture.The primary motivation for this approach was the fairly large similarity betweenthe Tinker, and the IA-64 architectures. Besides, Tinker is an experimental VLIWarchitecture that supports a number of features to exploit instruction level parallelism(ILP) and can be easily extended to support new features. This makes the back-endfor Tinker an ideal compiler to retarget for the IA-64 architecture, since it alreadyperforms most ILP optimizations that are supported on the IA-64.
Date: 2000-08-11
Degree: MS
Discipline: Computer Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/2934

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