Packet Processing on Stream Architecture

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dc.contributor.advisor Dr. Gregory T. Byrd, Committee Chair en_US
dc.contributor.advisor Dr. Yan Solihin, Committee Member en_US
dc.contributor.advisor Dr. W. Rhett Davis, Committee Member en_US
dc.contributor.advisor Dr. Khaled Harfoush, Committee Member en_US Lai, Yu-Kuen en_US 2010-04-02T18:25:41Z 2010-04-02T18:25:41Z 2006-07-24 en_US
dc.identifier.other etd-07062006-211628 en_US
dc.description.abstract Stream processing architectures have been proposed as efficient and flexible platforms for network packet processing. This is because packet processing shares many of the same characteristics of media and image processing that motivate stream architectures: little global data reuse, abundant data parallelism, and high computational complexity. This dissertation explores the SIMD (Single Instruction, Multiple Data) stream architecture for network packet processing with several security-related applications. The implementations are based on the stream programming model on the Imagine media processor, which consists of three tiers of memory hierarchy and eight VLIW clusters operating in SIMD mode. The applications explored are listed as follows: the Advanced Encryption Standard (AES)in parallel operation modes with key agility, theMultilinear Modular Hash (MMH) message authentication code, Bloom-filter-based content inspection engine for signature-based intrusion detection, and the sketch update for Internet traffic analysis. Some novel methodologies are also presented as applications being transformed and implemented on the stream architecture. The thesis characterizes the processing throughput of these applications and explores the tradeoffs on different configurations of stream architecture. Moreover, the sketch update application is also implemented on the Intel IXP network processor, in order to explore the difference between Imagine and a traditional architecture. The SIMD operation simplifies the access to shared data structure without explicit synchronization and arbitration overhead. As a result, the system achieves efficient utilization of maximum memory bandwidth. The architecture demonstrates the flexibility to support computation-intensive packet processing tasks at high performance. Applications such as hash and statistical based tasks are best fit into the stream programming model with an abundance of producer and consumer locality: portions of values computed and stored in the stream register file (SRF) are used for calculating a new set of values recursively. With a 500-MHz clock, the stream processor is capable of processing packets up to multi-gigabit-per-second throughput with outstanding power efficiency. Although packet processing over the SIMD stream architecture exhibits control flow and load balancing issues due to packet size variation, the analysis indicates that the multi-core, multi-SIMD architecture improves the performance and efficiency. Further explorations are proposed as promising directions for future research. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject network processor en_US
dc.subject stream processor en_US
dc.subject packet processing en_US
dc.subject network security en_US
dc.subject VLIW en_US
dc.subject SIMD en_US
dc.title Packet Processing on Stream Architecture en_US PhD en_US dissertation en_US Computer Engineering en_US

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