Analyzing and Managing Shared Cache in Chip Multi-Processors

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dc.contributor.advisor Yan Solihin, Committee Chair en_US
dc.contributor.advisor Eric Rotenberg, Committee Member en_US
dc.contributor.advisor Edward Gehringer, Committee Member en_US
dc.contributor.advisor Gregory Byrd, Committee Member en_US
dc.contributor.author Guo, Fei en_US
dc.date.accessioned 2010-04-02T18:28:12Z
dc.date.available 2010-04-02T18:28:12Z
dc.date.issued 2008-08-14 en_US
dc.identifier.other etd-07282008-162004 en_US
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.16/3234
dc.description.abstract Recently, Chip Multi-Processor (CMP) or multicore design has become the mainstream architecture choice for major microprocessor makers. In a CMP architecture, some important on-chip platform resources, such as the lowest level on-chip cache and the off-chip bandwidth, are shared by all the processor cores. As will be shown in this dissertation, resource sharing may lead to sub-optimal throughput, cache thrashing, thread starvation and priority inversion for the applications that fail to acquire sufficient resources to make good progress. In addition, resource sharing may also lead to a large performance variation for an individual application. Such performance variation is ill-suited for the future uses of CMPs in which many applications may require a certain level of performance guarantee, which we refer to as performance Quality of Service (QoS). In this dissertation, we address the resource sharing problem from two aspects. Firstly, we propose an analytical and several heuristic models that encapsulate and predict the impact of cache sharing. The models differ by their complexity and prediction accuracy. We validate the models against a cycle-accurate simulation. The most accurate model achieves an average error of 3.9%. Through a case study, we found that the cache sharing impact is largely affected by the temporal reuse behaviors of the co-scheduled applications. Secondly, we investigate a framework for providing performance Quality of Service in a CMP server. We found that the ability of a CMP to partition platform resources alone is not sufficient for fully providing QoS. We also need an appropriate way to specify a QoS target, and an admission control policy that accepts jobs only when their QoS targets can be satisfied. We also found that providing strict QoS often leads to a significant reduction in throughput due to resource fragmentation. We propose novel throughput optimization techniques that include: (1) exploiting various QoS execution modes, and (2) microarchitecture techniques that steal excess resources from a job while still meeting its QoS target. Through simulation, we found that compared to an unoptimized scheme, the throughput can be improved by up to 45%, making the throughput significantly closer to a non-QoS CMP. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dis sertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject QoS en_US
dc.subject Resource Stealing en_US
dc.subject Analyical Model en_US
dc.subject Performance Modeling en_US
dc.subject CMP en_US
dc.subject Cache en_US
dc.subject Memory en_US
dc.title Analyzing and Managing Shared Cache in Chip Multi-Processors en_US
dc.degree.name PhD en_US
dc.degree.level dissertation en_US
dc.degree.discipline Computer Engineering en_US


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