GaN MOSFETs for Low Power Giga Scale LSI Logic

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Title: GaN MOSFETs for Low Power Giga Scale LSI Logic
Author: Zeng, Chang
Advisors: Doug W. Barlage, Committee Chair
John F. Muth, Committee Member
Mark Johnson, Committee Member
Leda Lunardi, Committee Member
Robert M kolbas, Committee Member
Abstract: Advances in material quality and device processing have led to promising results for III-nitride electronic devices for high frequency applications. Numerous groups have report that GaN metal semiconductor field effect transistors (MESFETs) exhibit excellent device characteristics. However, a major concern of such devices is the leakage from the Schottky gate. As an alternative, the use of an insulated gate metal oxide semiconductor (MOS) structure reduces both gate leakage and power consumption. As described in this work, there are more potential advantages than reduced leakage by adopting a MOS structure in the III-N system. The scalability of this prototype device is shown with simulation to have the potential to support gate lengths below 10nm. In this Dissertation, methods to demonstrate a unique GaN based NMOS devices with minimum gate length of 0.7μm are described. Significant progress has been made on this challenging problem. The goal of this research is to introduce the processing methods and structures that will be suitable as a test vehicle for evaluating material interfaces in the GaN-Ga2O3-gate dielectric system. One of the aspects of this work is that a multi-wafer sapphire to device process time is less than one month. That enables the capacity to evaluate novel deposition schemes through electrical measurements in a timely manor. Furthermore, the process described here integrates re-grown GaN contacts. The pursuit of this is to allow maximum dopant incorporation and maximum abruptness in the source drain region to maximize the transistor's cut off frequency performance as well as the critical Ion performance. This process flow is also established as way to study hetero-geneous source drain properties. A method to analyze the n-i-n structure is presented in some detail. This n-i-n structure, along with the gate oxide, is the secondary key component to demonstrating a GaN MOS transistor with competitive performance properties for digital and RF applications. Of significance is the ability to fabricate a MOS device centered around the re-growth of N-type III-N material on intrinsically doped GaN. This method is directly related to the overall research goal to achieve a compound semiconductor MOSFET suitable for scaling below 10nm. This initial challenge of establishing a suitable experimentation vehicle has been met by the work described in this thesis. The intention of this work is to provide the experimental framework for the exploration of a variety of materials required to synthesize a complimentary GaN MOS system suitable for scaling to dimensions below 10nm.
Date: 2007-07-07
Degree: PhD
Discipline: Electrical Engineering

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