A Differential-Based Multiple Bit Rate PSK Receiver: Theory, Architecture, and SOI CMOS Implementation

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Title: A Differential-Based Multiple Bit Rate PSK Receiver: Theory, Architecture, and SOI CMOS Implementation
Author: Yuce, Mehmet Rasit
Advisors: Fuh-Gwo Yuan, Committee Member
Ralph Cavin, Committee Member
Numan Dogan, Committee Member
Wentai Liu, Committee Chair
Gianluca Lazzi,, Committee Member
Abstract: The development of telecommunications electronics with low-power and low-mass will be significant for future deep-space communications. The design of a receiver for deep-space communication requires the receiver to be robust against frequency variations due to Doppler effect in addition to radiation tolerance and low-power consumption. This dissertation reports a very low-power differential-based phase-shift keying (PSK) receiver that is targeted at deep-space and satellite communications, on both architectural and implementation levels. The power consumption of the PSK baseband circuit alone is less than 100 μW, which is significantly better than previously reported designs. Another major feature that has not been previously offered for PSK modulation is the use of 1-bit analog-to-digital converter (ADC) with sub-sampling front-end. The receiver uses double differential detection with traditional PSK modulation in the baseband to eliminate the impact of Doppler shift. Furthermore, the baseband can be employed in IF-sampling and direct sub-sampling front-end. Both front-ends offer minimal power consumption and differ from many traditional ones by eliminating some existing problems such as DC offset, dc voltage drifts and 1/f noise. The receiver also incorporates digital decimation stages to accommodate variable bit rates, and therefore it is highly programmable. The ability to support a wide range of data rates is an important feature of the receiver. This is achieved via digital channel selection by means of digital signal processing (DSP). The baseband and an analog part of the receiver are realized in 0.35 μm Silicon-on-Insulator (SOI) CMOS. SOI Complementary Metal Oxide Semiconductor (CMOS) technology is used mainly because it is a radiation hardness process. SOI technology is currently the most attractive choice in transceiver designs due to its advantages in both speed and power over standard CMOS because of lower parasitic capacitances. The designed baseband circuit consumes a power as low as 90.6 μW from a 1.1 V power supply. The analog part of the designed test chip consists of a two-stage differential IF amplifier that consumes a power of 0.8 mW from a 2.5 V supply. The primary goal of the proposed receiver is to achieve a higher integration at chip level, therefore resulting in significant size, power, and mass reductions for orbiter-lander communications while still meeting the system-level constraints.
Date: 2004-10-07
Degree: PhD
Discipline: Electrical Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/3642


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