Controller in Core: An Adaptive Microarchitectural Model for System-level Optimization

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dc.contributor.advisor Suleyman Sair, Committee Chair en_US
dc.contributor.advisor Thomas M Conte, Committee Member en_US
dc.contributor.advisor Yan Solihin, Committee Member en_US
dc.contributor.advisor Vincent Freeh, Committee Member en_US Gao, Fei en_US 2010-04-02T18:38:39Z 2010-04-02T18:38:39Z 2007-07-19 en_US
dc.identifier.other etd-07162006-223806 en_US
dc.description.abstract Modern processors are utilizing more complex microarchitectures to extract more Instruction Level Parallelism (ILP) ⁄ Thread Level Parallelism (TLP) to improve performance. In addition to performance concerns, power and thermal issues have also become important for microprocessor designers because of the increasing power/heat density and resulting cooling costs. Meanwhile, many runtime architectural optimization approaches, called adaptive microarchitectures, are proposed to optimize system resources dynamically based on the characteristics of applications. However, most of them focus on improving a specific microarchitecture component or metric. In this dissertation, we argue that system-wide optimization is the future of adaptive microarchitectures that can balance the tradeoffs between different optimization choices to achieve maximum overall performance. We propose a runtime optimization architectural model - Controller in Core (CiC), which uses a dedicated element to synthesize and analyze the system-wide runtime information and make judicious optimization decisions. To demonstrate the CiC model, we present a performance-oriented adaptive microarchitecture - an adaptive value predictor that tailors its value prediction functionality based on runtime system performance bottleneck analysis. We propose an event counter based performance model that can accurately estimate the performance cost for critical system events. Based on this model, we propose the bottleneck vector as the basis of long-term performance bottleneck analysis and a runtime bottleneck phase tracking scheme. In addition, three bottleneck phase prediction schemes are studied. Based on performance bottleneck analysis, we develop adaptation algorithms to control the adaptation of the adaptive value predictor. Our results show that the adaptive value predictor achieves 30% and 10% average performance gains when compared to the baseline and the traditional value predictor designs respectively. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject performance bottleneck en_US
dc.subject program phase en_US
dc.subject value prediction en_US
dc.subject adaptive microarchitecture en_US
dc.title Controller in Core: An Adaptive Microarchitectural Model for System-level Optimization en_US PhD en_US dissertation en_US Electrical Engineering en_US

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