Design of Pipeline Fast Fourier Transform Processors using 3 Dimensional Integrated Circuit Technology

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Title: Design of Pipeline Fast Fourier Transform Processors using 3 Dimensional Integrated Circuit Technology
Author: Sule, Ambarish Mukund
Advisors: Prof. Xun Liu, Committee Member
Prof. Paul Franzon, Committee Member
Prof. William Rhett Davis, Committee Chair
Prof. Steffen Heber, Committee Member
Abstract: Fast Fourier Transform (FFT) processing is an important component of many Digital Signal Processing (DSP) applications and communication systems. We focus on applications requiring large-point FFTs (>1024), and where high-speed of operation has priority. These range from Orthogonal Frequency Division Multiplexing (OFDM) based systems like Terrestrial Digital Video Broadcasting, very high speed digital subscriber loop systems and radar-based detection in military applications. We look at some of the popular FFT Architectures and compare their resource requirements and throughputs. We observe that the performance of pipelined large-point FFTs is limited due to the physical size and access times of the numerous First-in-First-out (FIFO) memories present in the design. For these pipeline FFTs, the critical path delay through arithmatic elements remains constant even as the number of stages increases, but the memory requirement almost doubles with every stage, thus increasing the memory access times in later stages. We demonstrate the advantage of using 3D Integrated Circuit Technology to assist in memory banks interleaving and stacking, leading to a boost in their performance. If the speed requirements for an application are less stringent, the same design could be tweaked and Vdd lowered to get a low power design. The 3DIC design methodology we use involves commercial single-tier CAD toolswith Perl, Python and TCL scripts to process their inputs and tie-up their single-tier outputs into a multi-tiered format. The design experiments utilize the 3-tier, 3-metal layer, fully depleted Silicon-on-Insulator 3D 0.18μm manufacturing process from MIT Lincoln Labs. Memory interleaving and stacking is demonstrated by the design of a 16KB FIFO which can run at 800Mhz. Finally, a design for an 8192-pt. FFT with 24 bits fixed-point inputs (12-bits each of real and imaginary) is proposed which uses the Radix-2⁄4⁄8 Multi-path Delay Commutator Pipelined Architecture and which can operate at 214 Mhz to give a new FFT set every 19μs.
Date: 2008-03-17
Degree: PhD
Discipline: Computer Engineering

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