Architectures and Design Methodology for Energy Efficient MIMO Decoders

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dc.contributor.advisor Dr. Xun Liu, Committee Member en_US
dc.contributor.advisor Dr. Ilse Ipsen, Committee Member en_US
dc.contributor.advisor Dr. Winser Alexander, Committee Member en_US
dc.contributor.advisor Dr. Paul Franzon, Committee Member en_US
dc.contributor.advisor Dr. William Rhett Davis, Committee Chair en_US
dc.contributor.author Jenkal, Ravi Somnath en_US
dc.date.accessioned 2010-04-02T18:39:49Z
dc.date.available 2010-04-02T18:39:49Z
dc.date.issued 2009-02-23 en_US
dc.identifier.other etd-11062008-130200 en_US
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.16/3897
dc.description.abstract This work focuses on the design and implementation aspects of Multi-Input Multi-Output (MIMO) decoders for multi-antenna communications. These decoders are used to determine, either optimally or sub-optimally, the bits encoded and transmitted over a wireless channel with more than one antenna. Present standards, such as 802.11n and 4G, call for systems with more than the present two antennas. Additionally, the need for future considerations of mobility along with lowered current limits of smaller technology nodes, calls for greater power awareness in the design of MIMO decoders. The presence of multiple antennas brings with them a) an exponentially large space for a min-cost search for the solution and b) non-trivial VLSI requirements to deal with additional dimensions of the wireless channel. Additionally, the conditions under which a MIMO decoder is used would change in terms of the Signal to Noise Ratio (SNR) values. This requires considerations in the multiple axes for a decoder implementation: Power, Delay, throughput and algorithmic performance. Of the many options available, Sphere Decoding (SD) has become a popular implementation of MIMO detection due to its improved performance at lower hardware complexity in comparison with Maximum Likelihood methods for optimal algorithmic performance. ASIC implementations have proven the feasibility of this method but fail to effectively address the issue of energy efficiency (b/s/mW). In this work, we investigate the architectural and design space of multi-antenna decoders. We show that systems that allow for tradeoffs along multiple axes are more likely to achieve energy optimality due to a changing usage environment. Multi-antenna systems are unique because they can exploit parallelism which could aid in amortizing the constraints on design. We design and implement improved architectures that exploit a combination of a deeper pipelines and simple single-port read and write memories to increase the energy efficiency (bits/sec/mW) of the decoding process. We also implement architectural modifications that increase the throughput of algorithmically optimal decoders. We use these improvements to make an argument for increased power consumption with the final aim of improving the energy efficiency of decoding. Additionally, we also provide insights into the design of architectures that can handle an increased constellation size and increased antenna numbers in a power efficient manner. In an effort to improve the throughput, we also provide a simple method of a block based algorithm using counters. VLSI implementation of all the architectures proposed provides the final measure of complexity in terms of power, area and throughput. The implementation of the proposed architectures in a 1.2V 90nm 8-metal IBM process demonstrates the effectiveness of the various methods proposed in reducing complexity and increasing energy efficiency. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dis sertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject VLSI en_US
dc.subject ASIC en_US
dc.subject Energy-efficient en_US
dc.subject MIMO en_US
dc.subject Architecture en_US
dc.subject Methodology en_US
dc.title Architectures and Design Methodology for Energy Efficient MIMO Decoders en_US
dc.degree.name PhD en_US
dc.degree.level dissertation en_US
dc.degree.discipline Computer Engineering en_US


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