Solving Complex Modeling of System-on-a-Chip (SOC) Test Automation and Optimal Resource Allocation by Neural Networks
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Date
2003-01-13
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Abstract
The objective of this research is to optimize the testing time and test resource allocation for System-on-a-Chip (SOC). The mathematical formulation and the neural networks with different techniques are proposed to solve these SOC test problems. First, a fixed-weight neural network combined with heuristic algorithms has been developed to solve the SOC test scheduling problems. The objective of this SOC test automation is to minimize the SOC testing time subject to different constraints: (i) precedence constraint, (ii) resource constraint, (iii) core constraint, and (iv) power constraint. Heuristic algorithms are often used to prevent the neural network from getting trapped in a local optima. The developed neural network can effectively solve the SOC test scheduling models with disjunctive constraints. The results show that the proposed method can efficiently solve a large-size SOC test scheduling problem within reasonable computing time. Second, to solve the resource allocation and the width selection problems for SOC test automation, a maximum neural network (MNN) has been proposed in this research for handling more complex SOC test problems. The SOC test automation problem with resource allocation is a NP-hard problem. The proposed maximum neural network can be used to solve the NP-hard SOC test problems within polynomial time. The results show that, by using the developed maximum neural network, the overall testing time for the SOC can be minimized with optimal resource allocation and test access mechanism (TAM) width selection. The computation time of the proposed method is significantly less than the time for traditional methods such as the integer linear programming (ILP) or heuristic algorithms. Third, the SOC test automation problems with core test wrapper design have been studied in this research. The core test wrapper design provides an interface between the core and the SOC in which the core is embedded. After the core test wrapper is designed, the total SOC testing time and the resource allocation for SOC test automation are optimized by using the developed maximum neural network. The proposed method is tested on five SOC benchmarks. The results show that it is possible to find the optimal SOC testing time of the complex SOC systems with shorter computation time than with the existing traditional methods. The techniques presented in this research can be used in test automation for System-on-a-Chip (SOC) design.
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System-on-a-Chip, neural networks, test scheduling, embedded core testing, semiconductor manufacturing
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Degree
PhD
Discipline
Industrial Engineering
