Algorithm Partitioning and Scheduling for Adaptive Computers

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Title: Algorithm Partitioning and Scheduling for Adaptive Computers
Author: Doss, Christopher
Advisors: Clay S. Gloster, Chair
Winser Alexander, Member
Thomas Conte, Member
Purush Iyer, Member
Abstract: Adaptive, or reconfigurable, computing has emerged as a viable computing alternative for computationally intense applications. (We use the terms adaptive and reconfigurable interchangeably). Here, an adaptive computer is a computing system that contains a general purpose processor attached to a programmable logic device such as a field programmable gate array (FPGA). These computing systems combine the flexibility of general purpose processors with the speed of application specific processors. The computer system designer can cater the hardware to a specific application by modifying the configuration of the FPGAs. The designer can reconfigure the FPGAs at some future time for other applications since the FPGAs do not have a fixed structure.Several reconfigurable computers have been implemented to demonstrate the viability of reconfigurable processors.Applications mapped to these processors include pattern recognition in high-energy physics, statistical physics and genetic optimization algorithms. In many cases, the reconfigurable computing implementation provided thehighest performance, in terms of execution speed, published (at the respective time).To achieve such performance, the application must effectively utilize the available resources. This presents a challenge for software designers, who are generally used to mapping applications onto fixed computing systems.Generally, the designers examine the available hardware resources and modify their application accordingly. With reconfigurable computers, the available resources can be generated when needed. While it may seem thatthis flexibility would ease the mapping process, it actually introduces new problems, such as what components should be allocated, and how many of each component should be used to generate the best performance. With conventionalhardware components, these questions were not an issue.In addition, software engineers are generally not adept at hardware design.In this dissertation, we present a design methodology for systematically implementing computationally intense applications on reconfigurable computing systems. This methodology is based on concepts from compiler theory to ease automation.In addition to the design methodology, we present, a toolthat implements a significant portion of the design methodology. RAS can be considered as a module generation tool for assisting the design process. Given a flow graph representing a loop nest, RAS allocates a set of resources, and schedules the nodes of the graph to the resources. RAS also generates an estimate of the amount of time it would take if the design implemented according to the schedule.This dissertation also presents results of designs produced by RAS. Multiple tests were performed using three computationally intense algorithms. RAS mapped the algorithms to five configurations representingdifferent sets of resource constraints. Two of the configurations were based on actual systems used in the research development, while the remainingthree were hypothetical systems based on other components available in the market. Experimental results from RASindicate that a significant amount of speedup is attainable using the allocated resources with the given schedule.
Date: 2001-06-27
Degree: PhD
Discipline: Computer Engineering

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