A MIMO Receiver SOC for CDMA Applications
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Date
2007-12-20
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Abstract
Multiple Input Multiple Output(MIMO) technique promises substantial increase of wireless channel capacity by using antenna arrays at both transmitters and receivers. It is one of the key technology to be used in the third generation wireless communication applications and is a current theme of international wireless research. Hardware implementation of MIMO receiver in today's wireless applications has stringent requirements such as high throughput, low power and high performance. This brings the difficulties to carry out the desired ASIC chip which is feasible to current silicon process.
In this thesis, we introduce a new System-on-a-Chip(SoC) design for the 3G Code Division Multiple Access(3G-CDMA) MIMO receiver. The SoC chip consists of a space-time equalizer, a MIMO detector and a turbo decoder onto a single chip, which can be configured to handle different modulation schemes including QPSK and 16QAM according to the signal-to-noise ratio(SNR). At low SNR, QPSK modulation scheme can provide lower bit error rate(BER), while at high SNR, 16QAM scheme can have a larger throughput. Sphere decoding algorithm is used for MIMO detection to achieve near maximum likelihood (ML) performance with relatively lower complexity for practical silicon implementation. To improve the system performance further, we implement a turbo decode, which decode the transmitted information bits using the soft decision result from the sphere decoder. Our design can achieve much lower BER than other current MIMO ASICs in the low SNR range. The paper also analyze the trade-off between the hardware complexity and the BER performance of the MIMO receiver using MATLAB fixed-point simulation and hardware synthesis.
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Keywords
CDMA, MIMO
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Degree
MS
Discipline
Electrical Engineering
