Fabrication and Device Characterization of Alternative Gate Stacks Using the Non Self-Aligned Gate Process
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2003-06-03
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In order to improve MOSFET transistor performance, aggressive scaling of devices has continued. As lateral device dimensions continue to scale down, gate oxide thicknesses must also be scaled down. According to the 2001 International Technology Roadmap for Semiconductor (ITRS) for sub-micron technology, an equivalent oxide thickness (EOT) less than 1.0 nm is required for high performance devices. However, at this thickness SiO₂ has reached its scaling limit due to the high tunneling current, especially in low power devcies. The use of high K dielectrics may circumvent this impediment since physically thicker dielectrics can be used to reduce gate leakage while maintaining the same level of inversion charge. In this study, we used an alternative, non self-aligned gate process to fabricate both NMOS and PMOS devices with a variety of high K gate dielectric and metal gate electrode materials; finally their electrical properties were characterized.
Most high K gate dielectric and gate metal candidates have limited thermal stability. As a result, conventional transistor fabrication process flows cannot be used. Here we developed a non self-aligned gate process, which reverses the order of the junction and the gate stack formation steps and thus allow the use of dielectrics and electrode materials that are not able to sustain high junction activation temperatures. A new mask set, ERC-6, was designed to facilitate the non-self aligned gate process.
Wet and dry etching process for alternative high K gate dielectrics (HfO₂, ZrO₂, La₂O₃, Y₂O₃) and metal gate electrodes (Pt, Ru, RuO₂, Ta, TaN) were studied. Wet etching of Pt and TaN required periodic re-baking of the photoresist to re-establish adhesion to the substrate. Reactive ion etch (RIE) processes were developed for RuO₂, Ru/W, Ta/W gate electrodes. A mixture of oxygen and fluorine plasma was effective in patterning RuO2 electrodes. However, for Ru gate electrodes, etch rates only up to 6.7 nm/min could be obtained even with the optimized addition of a few percent Cl₂ to O₂; this etch rate was considerably slower than that of photoresist. Rather than using a hard mask to etch the Ru gate, a laminated gate composed of a thin Ru layer (3 nm) covered with a thicker W film (100 nm) was successfully dry etched. The etching characteristics of various high K gate dielectrics depended not only on the materials, but also on how they were deposited, including the substrate pretreatment and post deposition anneal conditions. For instance, jet vapor deposited (JVD) HfO₂ would etch in BOE (10% HF), while other HfO₂ films required dry etching. Similarly, rapid thermal CVD (RTCVD) ZrO₂ required dry etching while other ZrO₂ films could be wet etched in BOE.
The electrical properties, including capacitance vs. voltage (C-V), gate leakage current (I[subscript g]-V[subscript g]), drain current vs. gate voltage (I[subscript d]-V[subscript g]) and drain current vs. drain voltage (I[subscript d]-V[subscript d]) characteristics, were measured on devices having a variety of high K gate dielectrics and gate metal electrodes. These electrical measurements were used to compare not only the different higk K dielectrics but also the different deposition systems. First, oxide control devices were fabricated to produce baseline data and to verify the non self-aligned process. The gate leakage current and channel mobility of the 1 nm thick control oxides were in good agreement with previously reported values. Reasonably good C-V characteristics were observed for HfO₂ (JVD) and ZrO₂ (JVD and RTCVD) except for the devices having TaN gate electrodes. Due to over-etching, a large die-to-die variability was observed with TaN gated capacitors. The measured EOT values for HfO₂ and ZrO₂ films ranged from 1.28 to 2.25 nm and 1.86 to 2.62 nm, respectively. The RTCVD HfO₂ and JVD ZrO₂ had the same gate leakage as reported values, while slightly higher leakages were observed with JVD HfO₂ and RTCVD ZrO₂. Nevertheless, most of the devices having HfO₂ or ZrO₂ dielectrics met the low operating power gate leakage specifications (0.81 A/cm² at 1.0 V) for the 100 nm and 70 nm ITRS technology nodes in our experimental splits. Devices made with physical vapor deposited (PVD) HfO₂ had the thinnest EOT (0.9 nm with Ru/W gate and 1.2 nm with poly-silicon gate).
The effect of forming gas annealing, 10% H₂ in 90 % N₂, on PVD HfO₂ was studied. We found that H₂ annealing showed significant enhancements in drive current and channel mobility. But even with H₂ annealing, HfO₂ still had lower mobility than high quality SiO₂. In order to further enhance its interface quality, D₂ forming gas annealing, 10% H₂ in 90 % N₂, was performed. Even though the detailed mechanism has not been revealed, D₂ annealing gave a greater increase in device current and mobility than H₂.
The gate leakage characteristics of HfO₂ and Hf silicate with poly-silicon and metal gates were measured and compared. For both HfO₂ and Hf silicate, large device-to-device gate leakage variations were observed with poly-silicon gate electrodes. In contrast to the poly-silicon gate devices, relatively small variations were observed with metal gates, where the gate leakages scaled with area. The statistical variations of gate leakage for poly-silicon and metal electrodes clearly showed that HfO₂ and Hf silicate degrade during the poly-silicon process. Experiments were designed with Hf silicate dielectrics to separately examine the thermal degradation during the high temperature poly-silicon activation cycle and chemical reaction during and after the poly-silicon CVD process. Al gated Hf silicate devices revealed no significant degradation even with pre-metal annealing temperatures up to 1000° C. Devices having different sources of poly-silicon gates (LPCVD poly-silicon, LPCVD amorphous silicon, and sputter deposit amorphous silicon) and metal gates were compared to examine the chemical reactions with the poly-silicon. Regardless of the depositions method, all devices with poly-silicon gates showed considerable degradation. Even though the high thermal budget itself had a negligible effect, the combination of high temperature annealing and the presence of silicon gates degraded Hf-based dielectrics.
The gate leakage of Hf silicate measured as a function of composition. The leakage current showed a minimum at an intermediate silicate composition (~ 50 %), verifying theoretical predictions. To retard additional oxidation during processing, nitridaiton was performed at the bottom interface or on the surface of Hf silicate dielectrics. Both of these nitridation steps influenced the final EOT and charge in the Hf silicate. Surface nitridiaion resulted in 10 % lower EOT than un-nitrided films, while interfacial nitridaion gave more effective reduction (~2 nm) in EOT. Interfacial and surface nitridation removed positive charges. On the other hand, surface nitridation alone introduced positive charges into the Hf silicate dielectrics.
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Keywords
device integration, metal gate electrode, high K dielectric, non-self aligned gate process
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Degree
PhD
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Materials Science and Engineering
