Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors

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Title: Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors
Author: Li, Wenmei
Advisors: Dennis M. Maher, Chair
John J. Hren, Member
Gerald Lucovsky, Member
Veena Misra, Member
Abstract: The purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-k dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterization methodologies were established to evaluate high-k dielectrics at various processing levels, which, in part, determine the final characteristics of an advanced gate-stack device. Material systems that were investigated include: Al-O, Hf-Si-O, Zr-Si-O, Ti-O, Ta-O and Sr-Ti-O. Various physical and electrical characterization techniques were used to establish fundamental understandings of the materials selected, thin-film growth/deposition processes, and gate-stack structures. General conclusions for stable and unstable gate-dielectric materials have been establishedregarding the presence of a problematic interfacial layer at the Si/dielectric interface, graded dielectric layers, and the stability of gate electrodes on high-k dielectrics.The nanometer-scale chemistry of a gate-stack capacitor whose expected structure is Si/SiOxNy/Ta2O5/TiN/Al was studied by high-resolution electron-energy-loss spectroscopy in a scanning transmission electron microscope. Elemental profiles with near-atomic-level resolution for Si, Ti, N, Al, and O demonstrate that the device structure deviates drastically from the expectation and is chemically complex.It is concluded that the graded distribution of certain elements across the gate-stack capacitor completely precludes a band-structure model that assumes abrupt interfaces and chemically discrete layers. This study impacted on subsequent interpretations of flatband voltage extractions and electrical degradation following backside metallization/postmetallization annealing for capacitors whose dielectric-stack was based on Ta-O.Detailed and extensive electrical characterizations of Pt/SiOx/Sr-Ti-O/Si MOS capacitors were carried out to investigate reliability issues in a bi-layer gate dielectric. Based on these studies, models are proposed to describe the carrier transport and dielectric degradation for a Sr-Ti-O capacitor. It is concluded that conduction is dominated by Frenkel-Poole emission from mid-gap trap levels. The trap barrier height is estimated to be 1.51eV. A model based on the atomic and electronic structure of oxygen vacancies can account for the reported leakage-current characteristics. In addition, it is tentatively proposed that anode-hole injection and hole trapping control the dielectric degradation under gate injection.
Date: 2001-02-05
Degree: PhD
Discipline: Materials Science and Engineering

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