Memory Intensive Architectures for DSP and Data Communication

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Title: Memory Intensive Architectures for DSP and Data Communication
Author: Mehrotra, Pronita
Advisors: Prof. Douglas Reeves, Committee Member
Prof. Gregory Byrd, Committee Member
Prof. Tom Conte, Committee Member
Prof. Paul Franzon, Committee Chair
Abstract: We focus on the design of systems where memory performance is the principal bottleneck. Two kinds of systems have been considered, an FFT engine for use in high performance DSP systems and forwarding engines used in high-speed routers. The FFT engine was designed using Seamless High Off-Chip Connectivity (SHOCC), a high-density interconnect and packaging technology. The SHOCC substrate was analyzed for different substrate stack-ups to determine the I/O bandwidth attainable by the technology. The FFT engine was designed to make full use of this available bandwidth. It provides for rotation of data to maintain a constant stride between stages, ensuring a constant data access pattern between different stages of the FFT. Data is twiddled before storing in memory, and an efficient scheduling algorithm allows generation of twiddle factors on-chip in parallel with other operations. The memory controller uses a novel memory-mapping scheme to avoid precharge and refresh penalties in DRAMs and achieves SRAM-like access speeds. Forwarding engines in IP routers need to perform a longest-matching-prefix search on the routing database. Two types of forwarding schemes are presented, a hardware-implementable trie based scheme and software implementations of modified binary searches. The hardware trie-based scheme uses a small amount of on-chip SRAM along with an off-chip DRAM (which stores the complete forwarding table). Only a single DRAM access is required to determine the next hop address. The binary search schemes store an additional field in the forwarding database to avoid any backtracking while searching for prefixes.
Date: 2002-09-01
Degree: PhD
Discipline: Electrical Engineering

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