Coupled Chip-to-Chip Interconnect Design

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Title: Coupled Chip-to-Chip Interconnect Design
Author: Luo, Lei
Advisors: Paul D. Franzon, Committee Chair
John M. Wilson, Committee Co-Chair
Michael B. Steer, Committee Member
W. Rhett Davis, Committee Member
Jon-Paul Maria, Committee Member
Abstract: In modern high performance VLSI chips high bandwidth and high throughput are becoming increasingly important. Multi-Tb⁄s throughput is the current trend of high performance VLSI chips. This trend demands high speed, high density and low power I⁄Os. AC coupled interconnect (ACCI) has been demonstrated as a systematic approach to provide higher pin density, smaller transceiver design and lower power dissipation for high speed chip-to-chip communications. ACCI utilizes non-contact capacitor plates as signal pins which yields a much higher pin density than traditional solder bump pins. The coupling capacitors provide passive equalization, thus eliminating the need for costly traditional active equalization. This saves both power and area associated with the equalization circuitry used in a traditional transceiver. ACCI also saves significant power on the transmitter by using pulse signaling instead of traditional non-return-to-zero (NRZ) signaling The pulse receiver is one of the most important designs in ACCI. The pulse receiver is used at receiver front end to recover the NRZ signal from the small pulse signal. A complementary low swing pulse receiver was designed to allow greater attenuation and to accommodate smaller coupling capacitors and longer transmission lines (T-Lines). A test chip with a complete capacitively coupled serial link was designed; including random data generator, multi-phase DLL, serializer, transmitter, pulse receiver, clock and data recovery (CDR), deserializer and bit error rate (BER) tester. ACCI chip-to-chip communication was demonstrated through two 150fF coupling capacitors and a single end terminated 15 cm microstrip line on a FR4 board at 3Gb⁄s. A differential pulse receiver is proposed for ACCI bus. The design and measurements of the proposed 36Gb⁄s receiver which operated over the 6-bit wide ACCI bus were reported. Signal integrity issues associated with the ACCI bus, such as crosstalk and switching noise, are discussed. Simulation results demonstrated that a higher data rate over ACCI channel can be achieved with more advanced CMOS technologies.
Date: 2006-12-13
Degree: PhD
Discipline: Electrical Engineering

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