Driver Pre-emphasis Signaling for On-Chip Global Interconnects

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dc.contributor.advisor Douglas S Reeves, Committee Member en_US
dc.contributor.advisor Paul D Franzon, Committee Chair en_US
dc.contributor.advisor Gianluca Lazzi, Committee Member en_US
dc.contributor.advisor John M Wilson, Committee Co-Chair en_US
dc.contributor.advisor W Rhett Davis, Committee Member en_US Zhang, Liang Leon en_US 2010-04-02T19:22:14Z 2010-04-02T19:22:14Z 2006-12-29 en_US
dc.identifier.other etd-12282005-225515 en_US
dc.description.abstract Signaling design for high performance VLSI systems has become an increasingly difficult task due to the delay⁄noise limitation for on-chip global interconnects. Repeater insertion techniques are widely used to improve the signal bandwidth of interconnect channels and to meet the delay goal of cross-chip communication, but even with a suboptimal delay approach, repeaters still consume a significant amount of power and area. They also increase the complexity of chip layout. As technologies continue to scale and operating frequencies continue to increase, the number of repeaters required increases exponentially. The intrinsic delay latency from repeaters themselves undermines total signal delay improvement. The techniques proposed to avoid or minimize repeaters, as well as the challenge of on-chip global interconnects, are reviewed. A simplified delay design guideline is derived to determine whether inductive effects are important for the long on-chip interconnects used in this work (i.e. whether distributed RC or RLC model should be chosen). Equalization techniques are verified as a capable solution to replace repeater insertion in achieving lower latency and higher data throughput for on-chip communication. A circuit for driver pre-emphasis is proposed by combining equalization techniques with a traditional voltage-mode on-chip bus driver. It is demonstrated in 0.18um CMOS technology for 10mm long interconnects at 2Gb⁄s. When compared to conventional repeater insertion techniques, driver pre-emphasis decreases repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. To further improve the bandwidth and noise performance of on-chip interconnect channel, the combination of driver pre-emphasis and current-mode differential signaling is also explored in this work. A 32Gb⁄s 16-bit bus is demonstrated in 0.25um CMOS technology. It reduces power by 15.0% at data activity factor of 0.1 and decreases peak current by 70%. The design is significantly less sensitive to crosstalk and delay variation, and occupies routing area comparable with conventional single-ended voltage-mode static buses. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject Equalization en_US
dc.subject Global interconnects en_US
dc.subject On-chip en_US
dc.subject Low-power en_US
dc.title Driver Pre-emphasis Signaling for On-Chip Global Interconnects en_US PhD en_US dissertation en_US Electrical Engineering en_US

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