Next Generation Power Factor Correction (PFC) Regulator Based on Silicon Carbide (SiC) Power Devices and New Control Strategy

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Title: Next Generation Power Factor Correction (PFC) Regulator Based on Silicon Carbide (SiC) Power Devices and New Control Strategy
Author: Xu, Xiaojun
Advisors: Dr. Kevin G. Gard , Committee Member
Dr. Subhashish Bhattacharya, Committee Member
Dr. Doug Barlage, Committee Member
Dr. Alex Q. Huang, Committee Chair
Abstract: As information and semiconductor technologies continue to develop, power supplies for applications such as telecommunications and computer systems are required to have higher power ratings, smaller volumes, and higher transfer efficiencies. The PFC stage, a key component of distributed power systems present in the front end of AC/DC converters, is an excellent target for increasing the power density and efficiency of the power supply, as it contains several large passive components. However, conventional commercial PFC designs are constrained by several limitations that prevent them from achieving the desired high power densities and efficiencies. In this dissertation, multiple techniques have been investigated to improve the power density and power efficiency of PFC boost converters. For a Continuous Conduction Mode (CCM) PFC converter, increasing the switching frequency at which the converter operates can dramatically reduce the volume of the boost inductor, while the EMI filter size can be reduced if the switching frequency is higher than 400kHz. To achieve high frequency operation, cutting edge SiC power devices are promising candidates for implementation into CCM PFC converters operating at switching frequencies into the MHz range due to their small on-state resistance and junction capacitance. Theoretical analysis and experimental results prove that extremely high power density can be obtained in a single phase 1MHz CCM PFC converter with SiC power devices, however, this converter’s efficiency falls short of the 95% efficiency target. A good compromise between high power density and power efficiency is achieved by employing multiphase interleaving architecture and SiC power devices simultaneously. This dissertation proposes novel nonlinear control architecture to simplify the controller design of multiphase interleaved CCM PFC regulators. PFC converters operating in Critical Mode (CRM) achieve high power efficiency by employing soft switching techniques, but the relatively large EMI filter required by this design prevents a single phase CRM converter from obtaining high power density because of the large input ripple current and low frequency harmonics. Multiphase interleaving architecture has been reported to be a practical way to improve the power density and output power rating of a CRM PFC converter. However, implementing multiphase interleaving design with variable switching frequency control is challenging because there is no clock signal available for synchronization. A novel closed loop interleaving technique is presented to achieve a precise phase shift, guaranteed critical mode operation, fast phase regulation, and ease of circuit implementation. To analyze the converter’s stability with this closed phase regulation loop, a new full order averaged model that considers the frequency variation and sample and hold delay is derived and verified in the SIMPLIS simulator. A CRM two phase interleaved converter prototype was constructed to demonstrate the viability of multiphase interleaving design; this converter exhibits continuous input current, ultra-fast phase regulation, robust critical mode operation, and a much higher power density than conventional designs.
Date: 2008-12-04
Degree: PhD
Discipline: Electrical Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/5940


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