Implementation of the Two Dimensional Integer Wavelet Transform for Transmission of Images

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Title: Implementation of the Two Dimensional Integer Wavelet Transform for Transmission of Images
Author: Joseph, Smitha
Advisors: Dr. W. Rhett davis, Committee Member
Dr. Wesley E. Snyder, Committee Member
Dr. Winser E. Alexander, Committee Chair
Abstract: Applications like telemedicine require the diagnostic information in the form of very large images to be transferred using existing networks. These applications use region of interest coding in medical images to reduce the cost while meeting the diagnostic quality requirements. The Integer Wavelet Transform is the major component in the JPEG 2000 based dynamic region of interest coding scheme. The wavelet transform helps to concentrate the signal energy to fewer coefficients to increase the degree of compression when the data is encoded. The wavelet transform is a computationally intensive component and the computations can be accelerated for real time applications like telemedicine by implementing the algorithm in hardware. Since the reconstruction of the medical images should be done with little or no loss to maintain diagnostic accuracy, we are interested in a lossless implementation of the wavelet transform. This thesis investigated the approaches to be used in the hardware implementation of the two dimensional integer wavelet lifting algorithm using the bi-orthogonal (9,7) filter. It proposes an implementation of a hardware model that meets the stringent quality requirements and is suitable for transmission of images for applications like telemedicine. The major design issues considered in the design of the 2D-integer wavelet transform architecture were the round off errors due to the use of fixed point arithemetic to perform the computations, the waiting time between the row and column processing, the memory access time and the implementation of the non-causal lifting structure. The round off errors in fixed point computations were reduced through scaling, sign extension and rounding. The proposed hardware model has a high throughput rate because it does the row and column processing in a single pass which avoids the waiting time between the row and column processing. This is done with substantial savings in memory over the more traditional level based designs. An architecture based on the data dependency graph was developed that overcame the difficulty posed by the non-causal lifting structure. The results obtained from the test cases on 8 bit gray scale images show that this 2D hardware model yields very good performance. The hardware model reconstructed the test images without any error.
Date: 2004-11-03
Degree: MS
Discipline: Electrical Engineering

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