A Study of Group III Elements (La, Gd, Eu, and Al) Incorporation on Metal Gate / High–k Stacks for Advanced CMOS Applications

Show simple item record

dc.contributor.advisor Dr. Doug W. Barlage, Committee Member en_US
dc.contributor.advisor Dr. Mehmet C. Ozturk, Committee Member en_US
dc.contributor.advisor Dr. Veena Misra, Committee Chair en_US
dc.contributor.advisor Dr. Steven C. Shannon, Committee Member en_US
dc.contributor.author Lee, Bongmook en_US
dc.date.accessioned 2010-08-19T18:14:31Z
dc.date.available 2010-08-19T18:14:31Z
dc.date.issued 2010-05-03 en_US
dc.identifier.other etd-03312010-115143 en_US
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.16/6186
dc.description.abstract The goal of this research is to evaluate the effect of group III elements incorporation into advanced metal gate / high–k dielectric stacks to achieve the desired gate stack work function without degrading electrical performance. The physical origins and possible mechanisms are provided in order to explain the experimental results. By incorporating group III elements into the gate stack, device VFB/VT can be modulated to the desired value for both NMOS (by using Rare Earth metals and oxide) and PMOS (by using an Al-based alloy) while maintaining key device properties. Based on these studies, an alternative route to achieve dual CMOS metal gate / high–k dielectric stacks for the next generation technology is demonstrated and supported with encouraging experimental results. The first part of this work focused on the impact of Rare-Earth metal incorporation on the effective work function of the gate stack by using Fully Silicided (FUSI) Gate approach. Rare-Earth metal incorporated Ni–FUSI gate on HfSiOx dielectric provides 0.3~0.4 V of effective work function shift depending on composition and metal. It was found that the structural properties with Gadolinium (Gd) and Europium (Eu) incorporation into Nickel (Ni) Fully Silicided (FUSI) gate electrodes are markedly different and resulted in different degrees of effective work function modulation. It was also found that the incorporation of Gd and Eu metals into Ni-FUSI gate can remotely scavenge the interfacial oxide layer resulting in lower EOT of the device. The second part of this work focused on the impact of Rare-Earth oxide capping on the electrical properties of NMOS devices. The presence of La atoms at high–k/SiO2 interface formed a dipole layer creating a band offset so that the effective work function of the gate stack is modulated toward NMOS band edge. It was found that the La concentration at high–k/SiO2 interface is the key factor for the VFB modulation whereas the host high–k materials and gate electrode on VFB shift have a minimal impact. In reliability, the incorporation of La2O3 can enhance both breakdown and PBTI characteristics since the La–induced dipole layer can effectively increase barrier height for electron injection as well as passivate some level of bulk defects in the HfO2 layer. The last part of this work addressed the impact of Al-based dielectric capping approach for PMOS devices. The addition of Ta in AlTaOx structure produces charges resulting in desired VT for PMOS devices as well as retarding Al diffusion through the HfO2 layer preventing Al–caused mobility degradation. Furthermore, the reliability characteristics such as breakdown and negative bias temperature instability (NBTI) were studied. The incorporation of an AlTaO capping layer improves device reliability characteristics by suppressing the hydrogen release as well as trap generation during the negative bias stress. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dis sertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.subject gate stack en_US
dc.subject reliability en_US
dc.subject advanced CMOS en_US
dc.subject high-k en_US
dc.subject metal gate en_US
dc.subject Vt tuning en_US
dc.subject work function en_US
dc.title A Study of Group III Elements (La, Gd, Eu, and Al) Incorporation on Metal Gate / High–k Stacks for Advanced CMOS Applications en_US
dc.degree.name PhD en_US
dc.degree.level dissertation en_US
dc.degree.discipline Electrical Engineering en_US

Files in this item

Files Size Format View
etd.pdf 3.015Mb PDF View/Open

This item appears in the following Collection(s)

Show simple item record