Benchmark Characterization of Embedded Processors
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Date
2005-05-16
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Abstract
The design of a processor is an iterative process, with many cycles of simulation, performance analysis and subsequent changes. The inputs to these cycles of simulations are generally a selected subset of standard benchmarks. To aid in reducing the number of cycles involved in design, one can characterize these selected benchmarks and use those characteristics to hit at a good initial design that will converge faster. Methods and systems to characterize benchmarks for normal processors are designed and implemented. This thesis extends these approaches and defines an abstract system to characterize benchmarks for embedded processors, taking into consideration the architectural requirements, power constraints and code compressibility. To demonstrate this method, around 25 benchmarks are characterized (10 from SPEC, and 15 from standard embedded benchmark suites - Mediabench and Netbench), and compared. Moreover, the similarities between these benchmarks are also analyzed and presented.
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processor design, benchmarks, benchmark characterization, embedded processors, SPEC2K, Mediabench, Netbench, WATTCH, simplescalar, power, code compression, Huffman encoder, recurrence conflict method, gshare predictor, branch prediction, IPC, TLB design, cache design, memory design, Kiviat graphs
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Degree
M
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Computer Science
