Design of a Self-test Vehicle for AC Coupled Interconnect Technology

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Title: Design of a Self-test Vehicle for AC Coupled Interconnect Technology
Author: Shah, Manav Rajendra
Advisors: Dr. W. Rhett Davis, Committee Member
Dr. Paul Franzon, Committee Member
Dr. John Wilson, Committee Chair
Abstract: The recent need for higher data rates has lead to the deployment of high density multi-gigabit interconnect technologies. AC coupling is one such technology which has been demonstrated to achieve high signaling speeds. With I/O interconnect speeds growing rapidly, engineers have to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. The quality of any interconnect technology, including its transceivers, can be analyzed by its BER (Bit Error Rate) performance. Traditionally, BER is evaluated using software simulations and stand-alone BER test products, which are either time-consuming orexpensive. We have developed a versatile BER testing system which exhibits advantages in speed and cost over existing solutions. In this thesis, we demonstrate the design and implementation of a self-contained FPGA-based system to test the AC coupled interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. The high speed BER logic is developed in verilog, while C-based drivers are written for an on-chip PowerPC processor to handle slow book-keeping tasks. An RS232 interface, which allows the user to remotely configure the system and obtain the BER results, is provided. The complete system is implemented and tested on an FPGA development board. The test system is evaluated on the basis of factors such as maximum operating speed, jitter specifications for the transceiver and intrinsic BER. Special recommendations for successful design of an 8-layer PCB (Printed Circuit Board) and the optimum selection of components are discussed. A complete schematic design of the ACCI test system is presented. This system will be used as a self-test vehicle on a low-orbit satellite to perform testing of AC coupled interconnects (including transceivers) and gather BER results. This thesis also serves as a base for developing complex test structures for high-speed interconnect protocols such as Infiniband, XAUI, PCI Express, Gigabit Ethernet, Fiber Channel etc. It should provide an interesting discussion for people trying to build test systems based on hardware/software co-design.
Date: 2006-04-24
Degree: MS
Discipline: Electrical Engineering

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