Memory Design for FFT Processor in 3DIC Technology

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Title: Memory Design for FFT Processor in 3DIC Technology
Author: Gonsalves, Kiran
Advisors: Dr. William Rhett Davis, Committee Member
Dr. Paul Franzon, Committee Chair
Dr. Eric Rotenberg, Committee Member
Abstract: Computation of Fast Fourier Transform (FFT) of a sequence is an integral part for the Synthetic Aperture Radar (SAR). For FFT computations, there are a lot of data modification operations (multiplication and addition) involved. Typically, a memory (either on-chip or off-chip) would store the input data packet and output data would also be written to the same location. This memory would also be used as a scratch pad for storing intermediate results. As the required resolution of the image increases, the size of the input data increases. Hence, the number of computations in the butterfly structure of the FFT increases and this results in numerous data transactions between the memory and the computation units. Each data access can be expensive in terms of power dissipation and access time. The power dissipation is proportional to the size of the memory and the access time is dependent on the electrical proximity of the memory to the processing unit. Three Dimensional Integrated Circuits (3D IC) enable the tight integration of this memory with the logic that operates on the memory. Apart from form-factor improvement, 3D IC technology's main advantage is that it significantly enhances interconnect resources. Davis et al. in mention that in the best case, if the inter-tier vias are ignored, the average wire length can be expected to drop by number of tiers raised to the power of 2. This structure is advantageous as it reduces the access time and enables quicker computation of FFT when compared to its two dimensional counterpart. Alternatively, when run at the same speed, the 3D version can be said to dissipate lower power than the 2D version, owing to smaller interconnect parasitics. The electrical proximity of the memory enables more interconnections (wider buses) and as a result, many number of small memories can be interfaced to the processing elements. This would not be possible in the conventional off-chip structure as the number of interconnect pins would be a limiting factor due to limitations on pin-outs and Printed Circuit Board (PCB) routing. This thesis supports the demonstration of memory on logic in a 3D IC environment by creating a full custom memory. The two types of memories designed for the application are Static Random Access Memory (SRAM) (for storing input, intermediate and output data) and Read Only Memory (ROM) (for storing twiddle factors for FFT computation). For the application a dual ported SRAM cell is sufficient with one port for read and another port for write purposes. The FFT algorithm used ensures that any location in the memory is never read from and written to at the same time and this eliminates the necessity for a design that protects against simultaneous read/write. The ROM is required to store elements that do not change during the calculation of the FFT, i.e. the twiddle factors. In this project, a 32 x 64 SRAM including multiplexers and 3D TSVs is designed. This can be readily integrated into a 3DIC flow. The area for the SRAM is 0.155 square mm, giving an area of 75.68 square microns per bit. The access time for the SRAM is 1.7ns. The energy for read access is 408.79 fJ/bit. The energy for write access is 90.78 fJ/bit. A 129 x 52 ROM is designed with 3D TSVs. This can be integrated into a 3DIC flow. The area for ROM is 0.032922 square mm, giving an area of 4.72 square microns per bit. The access time for the ROM is 1ns. The energy per access is 165 pJ/bit.
Date: 2009-03-18
Degree: MS
Discipline: Electrical Engineering

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