Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits

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Title: Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits
Author: Devasthali, Vinayak Sudhakar
Advisors: Dr.Paul Franzon, Committee Chair
Dr. Kevin Gard, Committee Member
Dr. W. Rhett Davis, Committee Member
Abstract: The efficiency of body biasing technique is evaluated in 90-nm process technology for regular and low threshold voltage devices. A new leakage monitor circuit for detecting an optimum reverse body bias voltage is designed. The simulation results shows that the monitor circuit accurately tracks the leakage currents within +/-5% of the actual leakage current values. The standby leakage reduction in static CMOS circuits using reverse body biasing is presented. The results indicate that the reverse body biasing is more beneficial for high speed circuits using low threshold voltage devices. For circuits using nominal threshold voltage devices, the efficiency of reverse body biasing decreases due to the presence of gate leakage. Speed improvement in ring oscillator and ripple carry adder using forward body bias is measured. The results show that the forward body biasing is less effective due to the lower body effect parameter. Supply voltage scaling technique for active power reduction is implemented using 180-nm technology. Power savings up to 50% is achieved by scaling the supply voltage as per the operating frequency requirements.
Date: 2008-12-20
Degree: MS
Discipline: Electrical Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/868


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