Design and Power Optimization of a 16 nm Dual Floating Gate FET Memory Array and Peripheral Circuits.

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Title: Design and Power Optimization of a 16 nm Dual Floating Gate FET Memory Array and Peripheral Circuits.
Author: Bhattacharyya, Abhishek
Advisors: Paul Franzon, Chair
Brian Floyd, Member
Gregory Byrd, Member
Date: 2013-08-05
Degree: Master of Science
Discipline: Computer Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/9115


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