Impact of Process Variations on 16-nm Dual-floating Gate FET using TCAD Simulations.
| Title: | Impact of Process Variations on 16-nm Dual-floating Gate FET using TCAD Simulations. |
| Author: | Kotipalli, Venkata Satya Vinodh |
| Advisors: | Paul Franzon, Chair Veena Misra, Member Neil DiSpigna, Member |
| Date: | 2012-12-18 |
| Degree: | Master of Science |
| Discipline: | Electrical Engineering |
| URI: | http://www.lib.ncsu.edu/resolver/1840.16/9208 |
Files in this item
| Files | Size | Format | View |
|---|---|---|---|
| etd.pdf | 1.505Mb |
View/ |