Versatile system for triple-gated transistors with engineered corners
| dc.date.accessioned | 2008-10-13T21:35:11Z | |
| dc.date.available | 2008-10-13T21:35:11Z | |
| dc.date.issued | 2005 | |
| dc.identifier.citation | Visokay, M. R., & Chambers, J. J. (2005). Versatile system for triple-gated transistors with engineered corners. U.S. Patent No. 6,969,644. Washington, DC: U.S. Patent and Trademark Office. | |
| dc.identifier.uri | http://www.lib.ncsu.edu/resolver/1840.2/1326 | |
| dc.format.extent | 115178 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en | |
| dc.title | Versatile system for triple-gated transistors with engineered corners | |
| dc.type | Patent |
Files in this item
| Files | Size | Format | View |
|---|---|---|---|
| US_6969644_B1_I.pdf | 112.4Kb |
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