Integrated circuit having reduced probability of wire-bond failure

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Title:	Integrated circuit having reduced probability of wire-bond failure
Date:	2000
Citation:	Kermani, B. G. (2000). Integrated circuit having reduced probability of wire-bond failure. U.S. Patent No. 6,153,506. Washington, DC: U.S. Patent and Trademark Office.
URI:	http://www.lib.ncsu.edu/resolver/1840.2/1643



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