Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal

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Title: Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal
Date: 2001
Citation: Fadavi-Ardekani, J., & Kermani, B. G. (2001). Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal. U.S. Patent No. 6,189,076. Washington, DC: U.S. Patent and Trademark Office.
URI: http://www.lib.ncsu.edu/resolver/1840.2/1666


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