Verilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark.

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Title: Verilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark.
Author: Vastrad, Adith Sagar
Advisors: Eric Rotenberg, Chair
James Tuck, Member
Huiyang Zhou, Member
Date: 2019-05-08
Degree: Master of Science
Discipline: Computer Engineering
URI: https://www.lib.ncsu.edu/resolver/1840.20/38089


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