Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing

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dc.contributor.author Nayani, Nirupama
dc.contributor.author Mollaghasemi, Mansooreh
dc.date.accessioned 2012-01-12T18:47:33Z
dc.date.available 2012-01-12T18:47:33Z
dc.date.issued 1998
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.4/5701
dc.format.extent 520560 bytes
dc.format.mimetype application/pdf
dc.format.mimetype application/pdf
dc.language.iso en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofseries Winter Simulation Conference Proceedings
dc.title Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
dc.type Technical report


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