Parallel Logic Level Simulation of VLSI Circuits

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dc.contributor.author Bagrodia, R.
dc.contributor.author Li, Z.
dc.contributor.author Jha, V.
dc.contributor.author Chen, Y.
dc.contributor.author Cong, J.
dc.date.accessioned 2012-01-12T18:50:27Z
dc.date.available 2012-01-12T18:50:27Z
dc.date.issued 1994
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.4/6602
dc.format.extent 1058529 bytes
dc.format.mimetype application/pdf
dc.format.mimetype application/pdf
dc.language.iso en
dc.publisher Institute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofseries Winter Simulation Conference Proceedings
dc.title Parallel Logic Level Simulation of VLSI Circuits
dc.type Technical report


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