Rotary Clock based High-Frequency ASIC Design Methodology

Abstract

With the increase of operating frequencies and dimensions, modern VLSI chips consume substantial power dissipation. For synchronous circuit designs, the clock network is a major power consumer, often contributing more than 20\% of overall power consumption. Consequently, power-efficient clock distribution methods have been extensively researched. In particular, the rotary clock technique is one low-power clocking approach that utilizes the LC oscillating principle to reduce power consumption. However, there are several design challenges that prevent the application of rotary technique.

In this dissertation, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design. Using our tool, linked various design parameters of a rotary clock design to its oscillation frequency and power dissipation. We then propose a power minimization algorithm. Our algorithm derives a rotary clock structure that dissipates the minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. We then developed a design methodology to implement the rotary clock based VLSI system. In particular, we present a circuit optimization scheme called skew spreading for rotary clock. Given an edge-triggered sequential circuit, skew spreading relocates the registers and derives the corresponding required clock arrival times, or skews, so that all skew values are distributed evenly in a preselected time window without changing the circuit functionality or the operating speed. We make the first attempt to design rotary based circuit by proposing a unified clock and circuit design methodology. Given a sequential circuit and a clock frequency, our scheme derives a rotary clock network and a functionally equivalent circuit so that they can be integrated to operate reliably at the target frequency. We have developed a physical design flow for rotary clock based design to address placement and timing issues. We have investigated the phase-locked-loop design under rotary clock technique. Our experiment results demonstrate that the charge-pump based PLL can be applied to to rotary clock network with 7% tuning range to cover the frequency deviation due to the process variations. Based on this design methodology, we have implemented a parallel transpose direct form 10-tap programmable FIR filter. Our experiment results show that in comparison with conventional clock tree based design we have achieved 12.8% total power savings and 34.6% clock tree network power savings without degrading the speed of circuits. In addition, the rotary clock based FIR filer has the peak current reduction of more than 40% with area degradation of less than 2% in comparison with clock tree based FIR filter design.