Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal
| dc.date.accessioned | 2008-10-16T16:47:59Z | |
| dc.date.available | 2008-10-16T16:47:59Z | |
| dc.date.issued | 2001 | |
| dc.format.extent | 143198 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | Fadavi-Ardekani, J., & Kermani, B. G. (2001). Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal. U.S. Patent No. 6,189,076. Washington, DC: U.S. Patent and Trademark Office. | |
| dc.identifier.uri | http://www.lib.ncsu.edu/resolver/1840.2/1666 | |
| dc.language.iso | en | |
| dc.title | Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal | |
| dc.type | Patent |
