Hardware Realization and Implementation Issues for the Sliding-window Packet Switch

Abstract

Shared memory packet switches are known to provide the best delay-throughput and respond well to bursty traffic. Shared memory switches are also known to scale poorly due to centralized control and memory bottlenecks. The Sliding Window Packet Switch (SW) algorithm is a shared memory switch that employs decentralized control and multiple memory modules to facilitate the scalability of hardware. The SW algorithm is independent of the type of packet or cell.

This research has two closely related goals. The first goal is to implement the SW algorithm in hardware such as an FPGA. This implementation is actually a specific case of the SW algorithm with four input ports and four output ports (i.e. a 4x4 switch). The second goal is to determine what scalability constraints exist in hardware for larger numbers of input and output ports (large NxN). These constraints are used to predict the overall throughput that the hardware implementation can handle.