Hardware Realization and Implementation Issues for the Sliding-window Packet Switch
| dc.contributor.advisor | Dr. Arne A. Nilsson, Committee Member | en_US |
| dc.contributor.advisor | Dr. Thomas M. Conte, Committee Member | en_US |
| dc.contributor.advisor | Dr. Paul D. Franzon, Committee Chair | en_US |
| dc.contributor.advisor | Dr. Sanjeev Kumar, Committee Member | en_US |
| dc.contributor.author | Phelps, Brian Roberson | en_US |
| dc.date.accessioned | 2010-04-02T17:58:52Z | |
| dc.date.available | 2010-04-02T17:58:52Z | |
| dc.date.issued | 2006-04-16 | en_US |
| dc.degree.discipline | Computer Engineering | en_US |
| dc.degree.level | thesis | en_US |
| dc.degree.name | MS | en_US |
| dc.description.abstract | Shared memory packet switches are known to provide the best delay-throughput and respond well to bursty traffic. Shared memory switches are also known to scale poorly due to centralized control and memory bottlenecks. The Sliding Window Packet Switch (SW) algorithm is a shared memory switch that employs decentralized control and multiple memory modules to facilitate the scalability of hardware. The SW algorithm is independent of the type of packet or cell. This research has two closely related goals. The first goal is to implement the SW algorithm in hardware such as an FPGA. This implementation is actually a specific case of the SW algorithm with four input ports and four output ports (i.e. a 4x4 switch). The second goal is to determine what scalability constraints exist in hardware for larger numbers of input and output ports (large NxN). These constraints are used to predict the overall throughput that the hardware implementation can handle. | en_US |
| dc.identifier.other | etd-03312004-152127 | en_US |
| dc.identifier.uri | http://www.lib.ncsu.edu/resolver/1840.16/854 | |
| dc.rights | I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. | en_US |
| dc.subject | sliding-window | en_US |
| dc.subject | packet | en_US |
| dc.subject | switch | en_US |
| dc.subject | scalability | en_US |
| dc.subject | hardware issues | en_US |
| dc.title | Hardware Realization and Implementation Issues for the Sliding-window Packet Switch | en_US |
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