Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System

Abstract

As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case, a higher modeling level of abstraction is need for designer to explore the design space at system level. Transaction-level model (TLM) is such an approach since it could run much faster than RTL model and also have enough accuracy. There are different modeling styles of TLM for different applications. In this thesis, we develop a hybrid-TLM of Network-on-chip (NoC) based on OSCI TLM-2.0 standard. We use a simplified version of the AMBA AXI protocol for the bus. This model contains a cycle-accurate AXI router and other periphery modules with approximately-timed coding style, which achieve fast simulation speed and accurate result. This model keeps good interoperability since it entirely based on TLM-2.0 standard. And the designer could build complex NoCs by making use of this model.