Computer Aided Tools for Seamless High Density Interconnects

Abstract

This thesis presents the tool-set designed to demonstrate the possibility of using the Cadence tools to design, verify and extract circuitry on the substrate along with theon-chip design. This circuitry could be an inter-chip connection that connects twodifferent chips or an intra-chip connection where a long interconnect is taken off fromthe active area of the chip to the substrate and back on to the same chip.

To be able to do this task, the work for this project is broadly classified into fourdifferent categories. These are writing

The technology file and the display.drf file The Design Rule Check deck The Layout Verses Schematic deck After having completed the above-mentioned tasks, the tool-set was also tested andimplemented on a circuit.