Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing

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dc.contributor.authorNayani, Nirupama
dc.contributor.authorMollaghasemi, Mansooreh
dc.date.accessioned2012-01-12T18:47:33Z
dc.date.available2012-01-12T18:47:33Z
dc.date.issued1998
dc.format.extent520560 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.4/5701
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofseriesWinter Simulation Conference Proceedings
dc.titleValidation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
dc.typeTechnical report

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