Hardware-Software Codesign of a Programmable Wireless Receiver System-on-a-chip

Abstract

With gate counts and system complexity growing rapidly, engineers have to find efficient ways of designing hardware circuits. The advent of Hardware Description Languages and synthesis methodologies improved designer productivity by raising the abstraction level. With advances in semiconductor manufacturing technology, however, there is still a growing productivity gap between the number of transistors-per-chip that can be fabricated and the transistors-per-day that can be effectively designed.

Increasing costs of design encourage reusing cores. Various kinds of Intellectual Property(IP) cores are now widely available and are used in making Integrated Circuits(IC). These System-on-a-chip(SOC) ICs generally contain a microprocessor as one of their IP cores in order to make them more exible. This heterogeneity of

hardware has increased challenges in verification. It is widely estimated that between 60%-80% of the design effort is dedicated to verifcation with almost half

of that time spent in construction and debugging of the simulation environments. Unfortunately, the high costs of industrial IP have made it difficult to explore SOC verification at Universities.

This thesis describes the building of a Programmable Wireless Receiver SOC using hardware-software codesign techniques. The SOC is comprised of a general purpose Central Processing Unit(CPU) and a baseband coprocessor with some glue logic. The CPU used is open-source, making it appropriate for teaching SOC verification as part of a university curriculum. The simulation environment adopted to verify the system and its documentation is an important product of this thesis. The thesis can be used

as a guideline for designing CPU-based SOCs.