Simulation of Memory Chip Line Using an Electronics Manufacturing Simulator

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dc.contributor.authorEstremadoyro, Douglas N.
dc.contributor.authorFarrington, Phillip A.
dc.contributor.authorSchroer, Bernard J.
dc.contributor.authorSwain, James J.
dc.date.accessioned2012-01-12T18:51:01Z
dc.date.available2012-01-12T18:51:01Z
dc.date.issued1997
dc.format.extent7284675 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.4/6803
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofseriesWinter Simulation Conference Proceedings
dc.titleSimulation of Memory Chip Line Using an Electronics Manufacturing Simulator
dc.typeTechnical report

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