Providing predictability for high end embedded systems

Abstract

Real-Time systems require logical and temporal correctness. Temporal correctness implies that each task running on the system has a deadline that needs to be met. To ensure that the deadlines are met, the scheduler of a real-time system needs information about the worst-case execution time (WCET) of each task. The task of determining the WCET of a task on a particular architecture is called timing analysis. Analysis techniques are broadly classified as static and dynamic. Dynamic timing analysis does not provide safe WCET bounds. Static analysis cannot be used on modern processors with features like out-of-order execution, dynamic branch prediction and speculative execution. Such features, while improving the average-case performance, induce counter-intuitive timing behavior known as timing anomalies. Hence, designers of hard real-time systems are forced to use architectures with simple in-order pipelines.

This thesis develops and demonstrates the benefits of a hybrid timing analysis technique (combining static and dynamic analysis) on a processor simulator and on FPGA hardware to provide tight and safe WCET bounds. The technique makes the following contributions:

* It enhances the realm of design for hard real-time systems by allowing the designers to use complex out-of-order architectures that exhibit timing anomalies. * It eliminates the need for complex prototyping of hardware for static timing analysis since the analysis can be done directly on the actual hardware. This has the added advantage of eliminating timing inaccuracies arising out of variations in manufacturing technology. * The method helps manufacturers to protect their Intellectual Property by eliminating the need to disclose architectural details for the purpose of static timing analysis.