Versatile system for triple-gated transistors with engineered corners

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dc.date.accessioned2008-10-13T21:57:11Z
dc.date.available2008-10-13T21:57:11Z
dc.date.issued2006
dc.format.extent127299 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationVisokay, M. R., & Chambers, J. J. (2006). Versatile system for triple-gated transistors with engineered corners. U.S. Patent No. 7,119,386. Washington, DC: U.S. Patent and Trademark Office.
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.2/1334
dc.language.isoen
dc.titleVersatile system for triple-gated transistors with engineered corners
dc.typePatent

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