Dynamically Reconfigurable Intrusion Detection System

Abstract

This dissertation implements a Network Based Intrusion Detection System on a Dynamically Reconfigurable Architecture. The design is captured using synthesizable Verilog HDL. The Dynamically Reconfigurable Intrusion Detection System (DRIDS) addresses the challenges faced by typical applications that use Reconfigurable devices that do not exploit their full computational density because of the limited FPGA memory, inefficient FPGA utilization, processor to FPGA communication bottlenecks and high reconfiguration latencies. The implementation of Intrusion Detection on the DRIDS boasts of high computational density and better performance through the exploitation of parallelism inherent in this application.