Fixed Charge Reduction and Tunneling in Stacked Dielectrics

Abstract

Stacked gate dielectrics using high-k materials were deposited using a RPECVD method. Aluminum oxide, hafnium oxide, hafnium silicate, nitrided films of each of the above, and multi-layer stacks of the above as well as silicon dioxide were deposited. These films were analyzed using AES, XPS, NRA, RBS, SIMS, XAS, cathodoluminescence, spectroscopic ellipsometry, capacitance-voltage, and current-voltage techniques. Fixed charge was found to be present in all high-k films and was practically impossible to reduce in a significant way. Nitridation of the films was unsuccessful at reducing the charge, but was helpful in enhancing some electrical measurements. Sandwich stack structures showed enhanced tunneling which led to a novel approach of calculating the E[subscript b]-m[subscript eff] product in the transmission probability equation. This tunneling also gives some clues as to which types of gate stacks cannot be used in technology. Gate stacks containing an HfO₂ layer below an Al₂O₃ layer were studied and also showed enhanced tunneling. Analysis of this tunneling found two significant trapping sites in the HfO₂ layer, one located ~0.5 eV below the HfO₂ conduction band offset and the other located in the Si bandgap. Fixed charge reduction was again expected in these laminates, but again remained despite theoretical predictions.