Design and Verification Methodology for Complex Three-Dimensional Digital Integrated Circuit

Abstract

Three-Dimensional Integrated Circuits (3DICs) have recently attracted great interest from researchers and IC designers as a possible solution to fill the gap between device and interconnect scaling. Various studies have demonstrated the potential performance improvement of 3DICs by eliminating long interconnects, repeaters, and clock buffers.

Though 3DICs are attractive, there are significant challenges associated with this topic. The most fundamental issue in 3DIC is heat dissipation. The thermal effect has impacted the conventional high-performance 2DICs in deep sub-micron technology nodes. Its effect will aggravate 3DICs due to two major reasons: higher power density, and lower thermal conductivity caused by more insulating dielectric layers. Furthermore, while 3D integration provides more design flexibility, this technology also introduces much higher design complexity. The existing 2D physical design methodology cannot be simply extended to a 3D case because of the huge obstacles in the z-direction and thermal constraints. Efficient design flows and algorithms must be developed to facilitate 3DIC design.

This dissertation proposes a design and verification methodology, along with analyses of delay, thermal, and reliability of a 3D system. The methodology uses commercial 2D CAD tools with Python and Tcl scripts to link them together. The scripts modify the output files (or databases) of the commercial tools and add 3D features to them. The entire flow achieves RTL-to-GDSII physical design automation for 3DICs.

Design trade-offs and timing reliability of 3D systems are two other major issues of this dissertation. Non-idealities threaten to diminish the benefit and may cause reliability problems in 3D systems. These non-idealities must be monitored during the design procedure. With a fast yet accurate temperature dependency model, these non-idealities were successfully taken into consideration during both design and verification phases. The final performance analyses of two benchmark circuits show that the 3DIC achieves a maximum reduction of 27% on energy and 20% on delay compared to the conventional 2DIC approach. Finally, a performance trend study of 3DIC as the technology node shrinks is also performed to guide future 3DIC designs.